Invention Grant
- Patent Title: Methods and apparatus to implement current limit test mode
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Application No.: US16670720Application Date: 2019-10-31
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Publication No.: US11095282B2Publication Date: 2021-08-17
- Inventor: Pavol Balaz
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Michelle F. Murray; Charles A. Brill; Frank D. Cimino
- Main IPC: H03K17/08
- IPC: H03K17/08 ; H03K17/0812 ; H02M3/07

Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.
Public/Granted literature
- US20200186142A1 METHODS AND APPARATUS TO IMPLEMENT CURRENT LIMIT TEST MODE Public/Granted day:2020-06-11
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