Methods and apparatus to implement current limit test mode
Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.
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