A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.