Invention Grant
- Patent Title: Systems and methods for power management of hardware utilizing virtual multilane architecture
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Application No.: US16528553Application Date: 2019-07-31
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Publication No.: US11150720B2Publication Date: 2021-10-19
- Inventor: Sateesh Kumar Addepalli
- Applicant: Sateesh Kumar Addepalli
- Applicant Address: US CA San Jose
- Assignee: Sateesh Kumar Addepalli
- Current Assignee: Sateesh Kumar Addepalli
- Current Assignee Address: US CA San Jose
- Agency: www.NielsenPatents.com
- Agent Steven A. Nielsen
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/3246 ; G06N5/04 ; G06N20/00 ; G06F1/3203

Abstract:
Aspects of the present disclosure are presented for a power management system of a multilane AI system architecture. The system may include an orchestrator configured to control power and other operations of a lane. An uber orchestrator manages the overall system, and may know all of the multilane systems within the AI virtual multilane system that need to be active at a given frequency and power envelope for given price, and performance constraints. The orchestrator of each lane knows the compute/logic blocks that need to be active for a given AI app model AI processing chain execution. The orchestrator may be configured to send commands to turn off power to certain components that are not utilized in performing an AI execution sequence, deactivate operation to the lane when its functions are completed, and also modulate the clock frequency of a lane to fit the computation demands while minimizing power usage.
Public/Granted literature
- US20200249743A1 SYSTEMS AND METHODS FOR POWER MANAGEMENT OF HARDWARE UTILIZING VIRTUAL MULTILANE ARCHITECTURE Public/Granted day:2020-08-06
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