A display panel includes a first scan driving circuit, a second scan driving circuit, and a third scan driving circuit. The first scan driving circuit is configured to generate a first gate scan signal to control programming of a first display line in a first horizontal sync period that includes a long horizontal blank (LHB) period. The second scan driving circuit is configured to generate a first dummy gate scan signal to control initialization of a second display line in the LHB period of the first horizontal sync period. The third scan driving circuit is configured to generate a second gate scan signal to control programming of the second display line in a second horizontal sync period that follows the first horizontal sync period.