- 专利标题: Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node
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申请号: US16245643申请日: 2019-01-11
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公开(公告)号: US11166363B2公开(公告)日: 2021-11-02
- 发明人: Antti Keränen , Tomi Simula , Mikko Heikkinen , Jarmo Sääski , Pasi Raappana , Minna Pirkonen
- 申请人: TACTOTEK OY
- 申请人地址: FI Oulunsalo
- 专利权人: TACTOTEK OY
- 当前专利权人: TACTOTEK OY
- 当前专利权人地址: FI Oulunsalo
- 代理机构: Carter, DeLuca & Farrell LLP
- 代理商 Robert P. Michal, Esq.
- 主分类号: H05K1/02
- IPC分类号: H05K1/02 ; H05K1/18 ; H05K5/06 ; H05K3/28
摘要:
An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.
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