- Patent Title: Self-aligned 3-D epitaxial structures for MOS device fabrication
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Application No.: US15668288Application Date: 2017-08-03
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Publication No.: US11171058B2Publication Date: 2021-11-09
- Inventor: Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L29/10 ; H01L21/8258

Abstract:
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
Public/Granted literature
- US20180019170A1 SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION Public/Granted day:2018-01-18
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