A stage of a scan driver for a display device, the stage includes: an output unit to output to an output terminal either a signal supplied to a first clock terminal corresponding to voltage of a first driving node or a voltage of a second power source corresponding to voltage of a second driving node; an input unit to control the voltage of the first driving node corresponding to signals supplied to a first input terminal, and the input unit to control the voltage of the second driving node corresponding to signals supplied to a second input terminal and a second clock terminal; a first signal processor including a second capacitor coupled between the second driving node and a second node, the first signal processor to control the voltage of the second driving node corresponding to signals supplied to a third clock terminal and a fourth clock terminal, the first signal processor to control a potential difference between both ends of the second capacitor corresponding to the signal supplied to the fourth clock terminal; and a second signal processor to control the voltage of the first driving node corresponding to the signal supplied to the first clock terminal.