- Patent Title: Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media
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Application No.: US14271812Application Date: 2014-05-07
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Publication No.: US11200058B2Publication Date: 2021-12-14
- Inventor: Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/50

Abstract:
Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
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