Invention Grant
- Patent Title: Processing method and device for cache synchronous exception
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Application No.: US16764849Application Date: 2018-10-29
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Publication No.: US11202227B2Publication Date: 2021-12-14
- Inventor: Jiamin Liu , Haiyang Quan
- Applicant: China Academy of Telecommunications Technology
- Applicant Address: CN Beijing
- Assignee: China Academy of Telecommunications Technology
- Current Assignee: China Academy of Telecommunications Technology
- Current Assignee Address: CN Beijing
- Agency: Kilpatrick Townsend & Stockton, LLP
- Priority: CN201711140664.8 20171116
- International Application: PCT/CN2018/112480 WO 20181029
- International Announcement: WO2019/095989 WO 20190523
- Main IPC: H04W28/04
- IPC: H04W28/04 ; H04L1/18 ; H04W28/06 ; H04W80/02

Abstract:
Disclosed in the present disclosure are a processing method and device for a cache synchronous exception, for solving the problem that no solution for a compression check failure is available in the prior art. According to embodiments of the present disclosure, when caches are out of synchronization, a caching failure notification message is sent to a transmitting device; a reset processing is carried out on a compressed cache area, and a reset instruction is sent; and then subsequent data packet transmission is carried out by using reset cache areas. In the present disclosure, after it is determined that the caches are out of synchronization, the caching failure notification message is sent; the transmitting device performs a reset processing on the compressed cache area, and notifies a receiving device to carry out a reset processing on a decompressed cache area.
Public/Granted literature
- US20200344644A1 PROCESSING METHOD AND DEVICE FOR CACHE SYNCHRONOUS EXCEPTION Public/Granted day:2020-10-29
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