Invention Grant
- Patent Title: Galvanic corrosion protection for semiconductor packages
-
Application No.: US16646932Application Date: 2017-12-30
-
Publication No.: US11217534B2Publication Date: 2022-01-04
- Inventor: Cheng Xu , Junnan Zhao , Ji Yong Park , Kyu Oh Lee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/069136 WO 20171230
- International Announcement: WO2019/133006 WO 20190704
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/00 ; H01L25/065 ; H01L23/498

Abstract:
Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
Public/Granted literature
- US20200266149A1 GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES Public/Granted day:2020-08-20
Information query
IPC分类: