The present application discloses a gate driver control circuit including an encoder configured to encode instruction information to obtain a coded instruction and to transmit the coded instruction. The gate driver control circuit further includes a decoder coupled to the encoder and configured to decode the coded instruction to obtain the instruction information. Additionally, the gate driver circuit includes at least one multiplexer coupled to the decoder. Each multiplexer is configured to receive a first set of multiple timing-control signals and the instruction information, to adjust the first set of multiple timing-control signals to a second set of multiple timing-control signals based on the instruction information, and to output the second set of multiple timing-control signals. The gate driver control circuit further includes at least one gate-array sub-circuit. Each gate-array circuit is configured to output multiple row-scanning signals in response to the second set of multiple timing-control signals.