- 专利标题： Monolithic chip stacking using a die with double-sided interconnect layers
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申请号： US16633543申请日： 2017-09-25
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公开(公告)号： US11251158B2公开(公告)日： 2022-02-15
- 发明人: Anup Pancholi , Kimin Jun
- 申请人： INTEL CORPORATION
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Essential Patents Group, LLP.
- 国际申请： PCT/US2017/053291 WO 20170925
- 国际公布： WO2019/059950 WO 20190328
- 主分类号： H01L25/065
- IPC分类号： H01L25/065 ; H01L21/56 ; H01L21/683 ; H01L23/00 ; H01L25/00
摘要：
An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
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