A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.