Invention Grant
- Patent Title: Method for manufacturing semiconductor structure with unleveled gate structure
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Application No.: US16667218Application Date: 2019-10-29
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Publication No.: US11271089B2Publication Date: 2022-03-08
- Inventor: Chai-Wei Chang , Che-Cheng Chang , Po-Chi Wu , Yi-Cheng Chao
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/423 ; H01L21/308

Abstract:
Methods for forming the semiconductor structure are provided. The method includes forming a fin structure and forming a gate dielectric layer across the fin structure. The method includes forming a work function metal layer over the gate dielectric layer and forming a gate electrode layer over the work function metal layer. The method further includes etching the work function metal layer to form a gap and etching the gate dielectric layer to enlarge the gap. The method further includes etching the gate electrode layer from the enlarged gap and forming a dielectric layer covering the gate dielectric layer, the work function metal layer, and the gate electrode layer. In addition, the dielectric layer includes a first portion, a second portion, and a third portion, and the first portion is thicker than the second portion, and the second portion is thicker than the third portion.
Public/Granted literature
- US20200066880A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH UNLEVELED GATE STRUCTURE Public/Granted day:2020-02-27
Information query
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