Invention Grant
- Patent Title: Methods and circuits for deadlock avoidance
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Application No.: US14530561Application Date: 2014-10-31
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Publication No.: US11281618B2Publication Date: 2022-03-22
- Inventor: Sagheer Ahmad , Tomai Knopp
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Crawford Maunu PLLC
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/16 ; G06F12/0831 ; G06F12/0804 ; G06F12/0888 ; G06F13/40

Abstract:
A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.
Public/Granted literature
- US20160124891A1 METHODS AND CIRCUITS FOR DEADLOCK AVOIDANCE Public/Granted day:2016-05-05
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