- 专利标题: Frequency bias correction for clock-data recovery in a serial data channel
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申请号: US17248753申请日: 2021-02-05
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公开(公告)号: US11283588B1公开(公告)日: 2022-03-22
- 发明人: Khitish Chandra Behera , Seid Alireza Razavi Majomard , Ragnar Hlynur Jonsson
- 申请人: Marvell Asia Pte, Ltd.
- 申请人地址: SG Singapore
- 专利权人: Marvell Asia Pte, Ltd.
- 当前专利权人: Marvell Asia Pte, Ltd.
- 当前专利权人地址: SG Singapore
- 主分类号: H04L7/02
- IPC分类号: H04L7/02 ; H04L7/00
摘要:
A physical layer transceiver for a serial data channel includes receiver circuitry having a local clock. Received signals arrive on the channel according to a remote clock. Clock-data recovery circuitry aligns the local clock with the remote clock by correcting phase and frequency error between the local and remote clocks. The clock-data recovery circuitry includes digital phase error detection circuitry operating according to a digital clock to detect phase error between the local and remote clocks, analog phase rotation circuitry to correct the detected phase error, distribution circuitry to divide the detected phase error into multiple phase error steps, and an analog clock source configured to provide the local clock to the analog phase rotation circuitry, and to provide to the distribution circuitry a distribution clock that is slower than the local clock, to correct the local clock by at least one step during one digital clock period.
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