Invention Grant
- Patent Title: Complementary cell circuits employing isolation structures for defect reduction and related methods of fabrication
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Application No.: US16798947Application Date: 2020-02-24
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Publication No.: US11295991B2Publication Date: 2022-04-05
- Inventor: Haining Yang , Junjing Bao
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: QUALCOMM Incorporated
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/762 ; H01L27/02 ; H01L27/092

Abstract:
To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.
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