Invention Grant
- Patent Title: Decoding for pseudo-triple-port SRAM
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Application No.: US17002010Application Date: 2020-08-25
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Publication No.: US11302388B2Publication Date: 2022-04-12
- Inventor: Arun Babu Pallerla , Changho Jung
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C11/418 ; G11C11/412 ; H03K19/20

Abstract:
A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.
Public/Granted literature
- US20220068369A1 DECODING FOR PSEUDO-TRIPLE-PORT SRAM Public/Granted day:2022-03-03
Information query
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