Invention Grant
- Patent Title: Die features for self-alignment during die bonding
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Application No.: US16993860Application Date: 2020-08-14
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Publication No.: US11302653B2Publication Date: 2022-04-12
- Inventor: Bret K. Street , Wei Zhou , Christopher J. Gambee , Jonathan S. Hacker , Shijian Luo
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.
Public/Granted literature
- US20200373252A1 Die Features for Self-Alignment During Die Bonding Public/Granted day:2020-11-26
Information query
IPC分类: