Invention Grant
- Patent Title: Interconnected stacked circuits
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Application No.: US16818792Application Date: 2020-03-13
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Publication No.: US11302672B2Publication Date: 2022-04-12
- Inventor: Didier Campos
- Applicant: STMicroelectronics (Grenoble 2) SAS
- Applicant Address: FR Grenoble
- Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee: STMicroelectronics (Grenoble 2) SAS
- Current Assignee Address: FR Grenoble
- Agency: Seed Intellectual Property Law Group LLP
- Priority: FR1902807 20190319
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L21/56 ; H01L21/768 ; H01L23/31 ; H01L23/00

Abstract:
The disclosure concerns an electronic device and methods of making an electronic device. The electronic device includes a circuit that is at least partially formed in an active region of a substrate. An electronic package is stacked on the substrate. A via extends through the circuit from the active region of the substrate to a surface of the substrate that is opposite the active region. At least one contacting element connects the via to the electronic package.
Public/Granted literature
- US20200303348A1 INTERCONNECTED STACKED CIRCUITS Public/Granted day:2020-09-24
Information query
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