A pixel driving circuit including: N pixel circuits each including a first node and a power supply terminal, N being an integer greater than 1; and N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits. A first one of the N multiplexing circuits includes a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits include respective multiplexing control circuits and respective reset circuits. The reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with a power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j