- 专利标题： Uniform gate width for nanostructure devices
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申请号： US16932476申请日： 2020-07-17
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公开(公告)号： US11315925B2公开(公告)日： 2022-04-26
- 发明人: Jui-Chien Huang , Shih-Cheng Chen , Chih-Hao Wang , Kuo-Cheng Chiang , Zhi-Chang Lin , Jung-Hung Chang , Lo-Heng Chang , Shi Ning Ju , Guan-Lin Chen
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L27/092
- IPC分类号： H01L27/092 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/8234
摘要：
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
公开/授权文献
- US20210066294A1 Uniform Gate Width for Nanostructure Devices 公开/授权日：2021-03-04
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