Invention Grant
- Patent Title: Low power methods for signal processing blocks in ethernet PHY
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Application No.: US17199142Application Date: 2021-03-11
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Publication No.: US11316707B2Publication Date: 2022-04-26
- Inventor: Kalpesh Laxmanbhai Rajai , Saravanakkumar Radhakrishnan , Gaurav Aggarwal , Raghu Ganesan , Rallabandi V Lakshmi Annapurna
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D Cimino
- Priority: IN202041010814 20200313
- Main IPC: H04L25/03
- IPC: H04L25/03 ; H04L12/12 ; H03H17/06

Abstract:
A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
Public/Granted literature
- US20210288826A1 LOW POWER METHODS FOR SIGNAL PROCESSING BLOCKS IN ETHERNET PHY Public/Granted day:2021-09-16
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