Invention Grant
- Patent Title: Vertical JFET device for memristor array interface
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Application No.: US17041382Application Date: 2018-04-27
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Publication No.: US11322545B2Publication Date: 2022-05-03
- Inventor: Amit S. Sharma , John Paul Strachan , Martin Foltin
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Houston
- Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee Address: US TX Houston
- Agency: McDermott Will & Emery
- International Application: PCT/US2018/029902 WO 20180427
- International Announcement: WO2019/209330 WO 20191031
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L27/24 ; H01L29/161 ; H01L29/808

Abstract:
Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.
Public/Granted literature
- US20210036058A1 VERTICAL JFET DEVICE FOR MEMRISTOR ARRAY INTERFACE Public/Granted day:2021-02-04
Information query
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