Invention Grant
- Patent Title: Vertical memory devices having contact plugs vertically extending through plurality of gate electrodes and contacting lower circuit pattern
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Application No.: US16819907Application Date: 2020-03-16
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Publication No.: US11335697B2Publication Date: 2022-05-17
- Inventor: Kohji Kanamori , Min-Yeong Song , Shin-Hwan Kang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2016-0056153 20160509
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11565 ; H01L27/11573 ; H01L27/11575 ; H01L27/06

Abstract:
A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.
Public/Granted literature
- US20200219898A1 VERTICAL MEMORY DEVICES Public/Granted day:2020-07-09
Information query
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