Invention Grant
- Patent Title: Cavity spacer for nanowire transistors
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Application No.: US16023511Application Date: 2018-06-29
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Publication No.: US11342411B2Publication Date: 2022-05-24
- Inventor: William Hsu , Biswajeet Guha , Leonard Guler , Souvik Chakrabarty , Jun Sung Kang , Bruce Beattie , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; B82Y10/00

Abstract:
A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
Public/Granted literature
- US20200006478A1 CAVITY SPACER FOR NANOWIRE TRANSISTORS Public/Granted day:2020-01-02
Information query
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