Invention Grant
- Patent Title: Selective liner on backside via and method thereof
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Application No.: US16944263Application Date: 2020-07-31
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Publication No.: US11342413B2Publication Date: 2022-05-24
- Inventor: Lin-Yu Huang , Li-Zhen Yu , Chia-Hao Chang , Cheng-Chi Chuang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/78 ; H01L29/06 ; H01L23/528

Abstract:
A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.
Public/Granted literature
- US20210336004A1 Selective Liner on Backside Via and Method Thereof Public/Granted day:2021-10-28
Information query
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