Invention Grant
- Patent Title: Semiconductor package having a semiconductor die on a plated conductive layer
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Application No.: US16706414Application Date: 2019-12-06
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Publication No.: US11348863B2Publication Date: 2022-05-31
- Inventor: Jefferson Talledo
- Applicant: STMicroelectronics, Inc.
- Applicant Address: PH Calamba
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: PH Calamba
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/31 ; H01L23/00 ; H01L21/48 ; H01L21/56

Abstract:
In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.
Information query
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