- Patent Title: Semiconductor device comprising stacked oxide semiconductor layers
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Application No.: US17065635Application Date: 2020-10-08
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Publication No.: US11355645B2Publication Date: 2022-06-07
- Inventor: Shunpei Yamazaki , Daisuke Matsubayashi , Keisuke Murayama
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi
- Agency: Robinson Intellectual Property Law Office
- Agent Eric J. Robinson
- Priority: JP2012-091539 20120413
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/786

Abstract:
A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
Public/Granted literature
- US20210036159A1 SEMICONDUCTOR DEVICE Public/Granted day:2021-02-04
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