A system-on-chip is provided. The system-on-chip includes a system bus, a plurality of IP units connected to the system bus, a processor unit including a plurality of cores configured to control the plurality of IP units via the system bus, a monitoring unit configured to monitor a state of the processor unit, and an error detection unit configured to operate as a master device for the plurality of IP units and monitor a register in which error information indicating whether an error has occurred in each of the plurality of IP units is stored.