- 专利标题: Asymmetrical plug technique for GaN devices
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申请号: US16857049申请日: 2020-04-23
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公开(公告)号: US11373873B2公开(公告)日: 2022-06-28
- 发明人: Alexey Kudymov , LinLin Liu , Jamal Ramdani
- 申请人: Power Integrations, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Power Integrations, Inc.
- 当前专利权人: Power Integrations, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Christensen O'Connor Johnson Kindness PLLC
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L29/417 ; H01L29/778 ; H01L29/20 ; H01L29/205 ; H01L23/482 ; H01L21/285
摘要:
A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.
公开/授权文献
- US20200258749A1 ASYMMETRICAL PLUG TECHNIQUE FOR GAN DEVICES 公开/授权日:2020-08-13
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