Invention Grant
- Patent Title: Extended drain MOS with dual well isolation
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Application No.: US16931935Application Date: 2020-07-17
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Publication No.: US11387323B2Publication Date: 2022-07-12
- Inventor: Chin-yu Tsai , Guruvayurappan Mathur
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L27/092 ; H01L29/45 ; H01L29/78 ; H01L21/265 ; H01L21/8238 ; H01L21/225 ; H01L21/324 ; H01L21/285 ; H01L21/74 ; H01L29/66 ; H01L21/266

Abstract:
An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.
Public/Granted literature
- US20200350405A1 EXTENDED DRAIN MOS WITH DUAL WELL ISOLATION Public/Granted day:2020-11-05
Information query
IPC分类: