A peripheral circuit includes a data preparation circuit, configured to selectively import, to a row or column of the resistive random access memory (RRAM) crossbar array based on a first control signal, preprocessed data obtained by first preprocessing on first data that is input into the data preparation circuit, a data selection circuit, configured to selectively export second data from the row or column of the RRAM crossbar array based on a second control signal, and perform second preprocessing on the second data to obtain third data, a data reading circuit, configured to: perform a weight update control operation, and perform a max pooling operation on fourth data that is input into the data reading circuit, to obtain fifth data, and a reverse training computation circuit, configured to calculate an error and a derivative of sixth data that is input into the reverse training computation circuit.