Invention Grant
- Patent Title: Decoding system and physical layout for analog neural memory in deep learning artificial neural network
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Application No.: US16503355Application Date: 2019-07-03
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Publication No.: US11423979B2Publication Date: 2022-08-23
- Inventor: Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly , Han Tran , Kha Nguyen , Hien Pham
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP US
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C11/16 ; G06N3/06 ; G11C11/4074 ; G06F17/16
Abstract:
Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
Public/Granted literature
- US20200342938A1 DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK Public/Granted day:2020-10-29
Information query
