Invention Grant
- Patent Title: Subtractively patterned interconnect structures for integrated circuits
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Application No.: US17087519Application Date: 2020-11-02
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Publication No.: US11444024B2Publication Date: 2022-09-13
- Inventor: Kevin Lin , Noriyuki Sato , Tristan Tronic , Michael Christenson , Christopher Jezewski , Jiun-Ruey Chen , James M. Blackwell , Matthew Metz , Miriam Reshotko , Nafees Kabir , Jeffery Bielefeld , Manish Chandhok , Hui Jae Yoo , Elijah Karpov , Carl Naylor , Ramanan Chebiam
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/532 ; H01L23/528 ; H01L21/3213 ; H01L21/768

Abstract:
IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.
Public/Granted literature
- US20220139823A1 SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS Public/Granted day:2022-05-05
Information query
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