An integrated circuit includes an error correction code (ECC) encoder configured to generate a first set of check bits in response to a first set of data, a first set of inverters coupled to the ECC encoder and being configured to generate a second set of check bits in response to the first set of check bits, and a first memory cell array. The second set of check bits is inverted from the first set of check bits. The first memory cell array includes a first portion of memory cells configured to store the first set of data, and a second portion of memory cells coupled to the first set of inverters, and configured to store the second set of check bits.