- Patent Title: Redundancy resource comparator for a bus architecture, bus architecture for a memory device implementing an improved comparison method and corresponding comparison method
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Application No.: US17338291Application Date: 2021-06-03
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Publication No.: US11461252B2Publication Date: 2022-10-04
- Inventor: Simone Mazzucchelli
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: IT102020000016441 20200707
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/16 ; G06F12/02 ; G06F13/362
Abstract:
Disclosed herein is a redundancy resource comparator for a bus architecture of a memory device for comparing an address signal being received from an address signal bus and a redundancy address being stored in a latch of the memory device. Disclosed is also a corresponding bus architecture and comparison method.
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