Invention Grant
- Patent Title: Method of forming graphene and metallic cap and barrier layers for interconnects
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Application No.: US16714431Application Date: 2019-12-13
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Publication No.: US11462470B2Publication Date: 2022-10-04
- Inventor: Shin-Yi Yang , Ming-Han Lee , Shau-Lin Shue
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/532 ; H01L23/528 ; H01L21/768

Abstract:
A method for manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.
Information query
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