- 专利标题: Large panel displays with reduced routing line resistance
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申请号: US17143939申请日: 2021-01-07
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公开(公告)号: US11462608B2公开(公告)日: 2022-10-04
- 发明人: Shinya Ono , Chin-Wei Lin , Akira Matsudaira , Jiun-Jye Chang , Jung Yen Huang , Pei-En Chang , Rungrot Kitsomboonloha , Szu-Hsien Lee
- 申请人: Apple Inc.
- 申请人地址: US CA Cupertino
- 专利权人: Apple Inc.
- 当前专利权人: Apple Inc.
- 当前专利权人地址: US CA Cupertino
- 代理机构: Treyz Law Group, P.C.
- 代理商 Jason Tsai
- 主分类号: G09G3/3225
- IPC分类号: G09G3/3225 ; G09G3/3266 ; H01L27/32 ; H01L29/786 ; H01L27/12 ; H01L29/49
摘要:
An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.
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