Invention Grant
- Patent Title: Techniques for configuring a processor to execute instructions efficiently
-
Application No.: US16460615Application Date: 2019-07-02
-
Publication No.: US11487341B2Publication Date: 2022-11-01
- Inventor: Aniket Naik , Tezaswi Raja , Kevin Wilder , Rajeshwaran Selvanesan , Divya Ramakrishnan , Daniel Rodriguez , Benjamin Faulkner , Raj Jayakar , Fei (Walter) Li
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nixon & Vanderhye PC
- Main IPC: G06F1/324
- IPC: G06F1/324 ; G06F9/38

Abstract:
Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.
Public/Granted literature
- US20200050251A1 TECHNIQUES FOR CONFIGURING A PROCESSOR TO EXECUTE INSTRUCTIONS EFFICIENTLY Public/Granted day:2020-02-13
Information query