- Patent Title: Method of forming split gate memory cells with thinner tunnel oxide
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Application No.: US17179057Application Date: 2021-02-18
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Publication No.: US11488970B2Publication Date: 2022-11-01
- Inventor: Jeng-Wei Yang , Man-Tang Wu , Boolean Fan , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L27/11524
- IPC: H01L27/11524 ; G11C16/04 ; H01L29/66

Abstract:
A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
Public/Granted literature
- US20220013531A1 Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide Public/Granted day:2022-01-13
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