Invention Grant
- Patent Title: III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer
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Application No.: US16934669Application Date: 2020-07-21
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Publication No.: US11515397B2Publication Date: 2022-11-29
- Inventor: Anthony K. Stamper , Siva P. Adusumilli , Vibhor Jain , Steven Bentley
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/20 ; H01L29/778 ; H01L29/06 ; H01L21/763 ; H01L21/8234 ; H01L29/36
Abstract:
Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.
Public/Granted literature
- US20220029000A1 III-V COMPOUND SEMICONDUCTOR LAYER STACKS WITH ELECTRICAL ISOLATION PROVIDED BY A TRAP-RICH LAYER Public/Granted day:2022-01-27
Information query
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