- 专利标题: Accurately calculating multi-input switching delay of complemantary-metal-oxide semiconductor gates
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申请号: US16699285申请日: 2019-11-29
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公开(公告)号: US11520962B1公开(公告)日: 2022-12-06
- 发明人: Ahmed M. Shebaita , Han Y. Koh , Li Ding
- 申请人: Synopsys, Inc.
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys, Inc.
- 当前专利权人: Synopsys, Inc.
- 当前专利权人地址: US CA Mountain View
- 代理机构: Park, Vaughan, Fleming & Dowler LLP
- 代理商 Laxman Sahasrabuddhe
- 主分类号: G06F30/3312
- IPC分类号: G06F30/3312 ; G06F119/12 ; G06F30/398 ; H03K19/0948
摘要:
Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.
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