Invention Grant
- Patent Title: Method of manufacturing array substrate, and array substrate
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Application No.: US16964278Application Date: 2019-12-13
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Publication No.: US11537016B2Publication Date: 2022-12-27
- Inventor: Leilei Cheng , Jingang Fang , Luke Ding , Jun Liu , Wei Li , Bin Zhou
- Applicant: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. , BOE Technology Group Co., Ltd.
- Applicant Address: CN Anhui; CN Beijing
- Assignee: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.,BOE Technology Group Co., Ltd.
- Current Assignee: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.,BOE Technology Group Co., Ltd.
- Current Assignee Address: CN Anhui; CN Beijing
- Agency: Westman, Champlin & Koehler, P.A.
- Priority: CN201910108116.X 20190202
- International Application: PCT/CN2019/125208 WO 20191213
- International Announcement: WO2020/155887 WO 20200806
- Main IPC: G02F1/1333
- IPC: G02F1/1333 ; G02F1/1362 ; H01L21/768 ; H01L23/532 ; H01L27/12

Abstract:
A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.
Public/Granted literature
- US20210124226A1 METHOD OF MANUFACTURING ARRAY SUBSTRATE, AND ARRAY SUBSTRATE Public/Granted day:2021-04-29
Information query
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