Invention Grant
- Patent Title: Gate driver circuit for reducing deadtime inefficiencies
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Application No.: US17469444Application Date: 2021-09-08
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Publication No.: US11543846B2Publication Date: 2023-01-03
- Inventor: Krishnamurthy Ganapathi Shankar
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Main IPC: G05F3/26
- IPC: G05F3/26 ; H02H7/12 ; H02M3/07 ; H03K17/693 ; H03K17/62 ; H02P7/03

Abstract:
A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.
Public/Granted literature
- US20210405678A1 GATE DRIVER CIRCUIT FOR REDUCING DEADTIME INEFFICIENCIES Public/Granted day:2021-12-30
Information query
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