Invention Grant
- Patent Title: Error coalescing
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Application No.: US17363622Application Date: 2021-06-30
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Publication No.: US11544145B2Publication Date: 2023-01-03
- Inventor: John Eric Linstadt
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Neudeck Law Firm, LLC
- Main IPC: G06F11/10
- IPC: G06F11/10

Abstract:
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.
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