Invention Grant
- Patent Title: Memory circuit arrangement for accurate and secure read
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Application No.: US17321344Application Date: 2021-05-14
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Publication No.: US11551731B2Publication Date: 2023-01-10
- Inventor: Vikas Rana , Arpit Vijayvergia
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/06 ; H03K19/20

Abstract:
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
Public/Granted literature
- US20210375333A1 MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ Public/Granted day:2021-12-02
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