Invention Grant
- Patent Title: High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region
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Application No.: US16952500Application Date: 2020-11-19
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Publication No.: US11552190B2Publication Date: 2023-01-10
- Inventor: Edward John Coyne , Alan Brannick , John P. Meskell
- Applicant: Analog Devices International Unlimited Company
- Applicant Address: IE Limerick
- Assignee: Analog Devices International Unlimited Company
- Current Assignee: Analog Devices International Unlimited Company
- Current Assignee Address: IE Limerick
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/40 ; H01L29/66

Abstract:
A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.
Public/Granted literature
- US20210184033A1 HIGH VOLTAGE DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR Public/Granted day:2021-06-17
Information query
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