Invention Grant
- Patent Title: Methods for sub-lithography resolution patterning
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Application No.: US16989019Application Date: 2020-08-10
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Publication No.: US11557515B2Publication Date: 2023-01-17
- Inventor: Sony Varghese
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDB Firm PLLC
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface, and forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer. The mask may be formed over the plurality of patterning structures without being formed along the second sidewall. The method may further include selectively forming a metal layer along the second sidewall of each of the plurality of patterning structures.
Information query
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