Invention Grant
- Patent Title: Low power operational amplifier trim offset circuitry
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Application No.: US16701629Application Date: 2019-12-03
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Publication No.: US11558013B2Publication Date: 2023-01-17
- Inventor: Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Krista Y. Chan; Frank D. Cimino
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H03F3/45 ; H03M1/66

Abstract:
Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
Public/Granted literature
- US20210167731A1 LOW POWER OPERATIONAL AMPLIFIER TRIM OFFSET CIRCUITRY Public/Granted day:2021-06-03
Information query
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